1. Field of the Invention
This invention relates generally to fabrication of integrated circuit devices and, more particularly, to the fabrication of insulated-gate, field effect transistors that are electrically isolated from neighboring integrated circuit elements by isolation structures.
2. Description of the Related Art
An insulated-gate field effect transistor (IGFET) device 5, such as a metal-oxide semiconductor field-effect transistor (MOSFET), having isolation structures that electrically insulate the transistor from the surrounding portions of the integrated circuit is shown in FIG. 1. A substrate 10 has a doped well region 12, a p-doped well will be used for purposes of illustration. The substrate 10 has a p-doped channel region 14 that provides a conducting path between the n-doped source/drain regions 16A, 16B and the n-doped source/drain regions 18A, 18B. In addition, an n-doped punch-through region 20 is provided below the channel region 14. Also formed in the substrate are the isolation structures 22 and 24. The gate structure of the IGFET device 5 includes an gate dielectric 26, directly over the channel region 20 and a gate electrode 28 over the gate dielectric 26. The gate structures 26, 28 can include spacers 30, 32 formed against the walls of the gate structure. An insulating layer 34 covers the substrate 10 and the gate structure 26, 28. The insulating layer 34 has vias formed therein and the vias are filled with a conducting material 36. The conducting material 36 provides conducting paths to source/drain (electrode) regions 16A, 16B and 18A, 18B and to the gate electrode 28. An insulating layer 38 is patterned and patterned portions are filled with conducting material to provide conducting paths 40. The conducting paths 40 and the remaining insulating material 38 are the interconnect layer 38, 40 that provides the electrical coupling between the IGFET device 5 and the remainder of the integrated circuit.
The operation of the IGFET device 5 can be understood as follows. A voltage applied to the gate electrode 28 causes a transverse field in the channel region 14. The transverse field controls (e.g., modulates) the current flow between source/drain regions 16A, 16B and source/drain region 18A, 18B. The punch-through region 20 is formed to prevent parasitic effects that can occur when this region is not formed in the device 5. The spacers 30, 32 and the dual-structured doped source/drain regions 16A, 16B and 18A, 18B address a problem generally referred to as the "hot-carrier" effect. When only one source/drain region 16A and 18A is present and is formed by doping technique aligned with the electrode structure 26, 28, charge carriers from these regions will be migrate into the channel region 14 and be trapped by the gate dielectric 26. These trapped charge carriers adversely effect the transverse electric field normally formed in the channel region 14 by a voltage applied to the gate electrode 28. The problem is alleviated by lightly-doping source/drain regions 16A and 18A by a technique that aligns this doping procedure with the gate structure 26, 28. Spacers 30 and 32 are next formed on the walls of the gate structure 26, 28. Source /drain regions 16B and 18B are formed by a doping procedure, resulting in source/drain doping concentrations at normal levels, that aligns the source/drain regions 16B and 18B with the spacers 30 and 32, respectively. (while this two level doping procedure effectively eliminates the "hot-carrier" problem, the resistance between the two source/drain dual regions 16A, 16B and 18A, 18B is increased.) The isolation structures 22, 24 provide electrical insulation between device 5 and a remainder of the integrated circuit.
A need has been felt for an improved process for the fabrication of IGFET devices that includes electrical isolation structures. A desirable feature of the process would be the replacement of the local oxidation of silicon (LOCOS) process, a process that has in the past been used to create the electrical isolation regions, with a process for better control of the structure of the isolation region. Another desirable feature of the process would be the ability to provide self-aligned, lightly-doped source/drain regions for the IGFET device. A further desirable feature of the process would be the ability to provide a device structure that would result in a planar structure for the IGFET device.